c_like

std › riscv › c_like

RISC-V RV32I written as expressions instead of mnemonics: a0 = a1 + a2, a1 = mem[sp + 8], if (a0 != zero) goto loop.

from std.riscv.c_like import *

loop:
    a0 <- a0 + -1
    if (a0 != zero) goto loop
    a1 = mem[sp + 8]

13 05 f5 ff
e3 1e 05 fe
83 25 81 00

• A register-register operation uses =, and one with an immediate uses <-: a0 = a0 + a1 is add, and a0 <- a0 + 1 is addi.
• >>> is a logical shift right, and >> an arithmetic one.
• Loads and stores smaller than a word name their width before mem: i8, u8, i16 or u16.
• Unsigned comparisons (sltu, sltiu, bltu, bgeu), lui, auipc, ecall, ebreak, li, la and ascii have no C-like spelling, and keep their plain name a, b, c syntax.

Import this instead of std.riscv.native, never alongside it: both assign syntax to the same instructions.

Re-exports std.riscv.impl.

Macros

add

rd = rs1 + rs2.

sub

rd = rs1 - rs2.

sll

rd = rs1 << rs2, shifting by the low 5 bits of rs2.

slt

rd = 1 if rs1 < rs2 as signed numbers, else 0.

sltu

rd = 1 if rs1 < rs2 as unsigned numbers, else 0.

xor

rd = rs1 ^ rs2.

srl

rd = rs1 >> rs2, shifting in zeros, by the low 5 bits of rs2.

sra

rd = rs1 >> rs2, shifting in copies of the sign bit, by the low 5 bits of rs2.

or

rd = rs1 | rs2.

and

rd = rs1 & rs2.

addi

rd = rs1 + imm, with a 12-bit signed imm.

slti

rd = 1 if rs1 < imm as signed numbers, else 0.

sltiu

rd = 1 if rs1 < imm as unsigned numbers, else 0. imm is sign-extended first, so sltiu rd, rs1, 1 tests for zero.

xori

rd = rs1 ^ imm. xori rd, rs1, -1 is bitwise NOT.

ori

rd = rs1 | imm.

andi

rd = rs1 & imm.

slli

rd = rs1 << shamt, for shamt from 0 to 31.

srli

rd = rs1 >> shamt, shifting in zeros, for shamt from 0 to 31.

srai

rd = rs1 >> shamt, shifting in copies of the sign bit, for shamt from 0 to 31.

jalr

Jumps to rs1 + offset (with bit 0 cleared) and puts the address of the next instruction in rd. jalr zero, ra, 0 returns from a function.

ecall

Calls the execution environment, e.g. a Linux system call.

ebreak

Stops in a debugger.

lb

Loads the byte at rs1 + offset into rd, sign-extended.

lh

Loads the 16-bit halfword at rs1 + offset into rd, sign-extended.

lw

Loads the 32-bit word at rs1 + offset into rd.

lbu

Loads the byte at rs1 + offset into rd, zero-extended.

lhu

Loads the 16-bit halfword at rs1 + offset into rd, zero-extended.

sb

Stores the low byte of rs2 at rs1 + offset.

sh

Stores the low 16 bits of rs2 at rs1 + offset.

sw

Stores rs2 at rs1 + offset.

beq

Branches to the label target if rs1 == rs2.

bne

Branches to the label target if rs1 != rs2.

blt

Branches to the label target if rs1 < rs2 as signed numbers.

bge

Branches to the label target if rs1 >= rs2 as signed numbers.

bltu

Branches to the label target if rs1 < rs2 as unsigned numbers.

bgeu

Branches to the label target if rs1 >= rs2 as unsigned numbers.

lui

rd = imm << 12: loads a 20-bit upper immediate.

auipc

rd = pc + (imm << 12): an address relative to this instruction.

jal

Jumps to the label target and puts the address of the next instruction in rd. jal ra, f calls f; jal zero, l just jumps.

li

Loads the constant imm into rd: addi rd, zero, imm when it fits in 12 signed bits, else lui for the upper 20 bits then, unless they’re zero, addi for the rest.

la

Loads the address of the label symbol into rd: auipc for the upper 20 bits of the distance, then addi for the rest.

ascii

A string literal’s UTF-8 bytes, with no terminator: GNU’s .ascii.

Re-exported

From std.riscv.impl: Reg, x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, zero, ra, sp, gp, tp, t0, t1, t2, s0, fp, s1, a0, a1, a2, a3, a4, a5, a6, a7, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, t3, t4, t5, t6, Opcode, Funct3, Funct7, Bit1, Imm4, Imm5, Imm6, Imm7, Imm8, Imm10, Imm12, Imm20, RType, IType, SType, BType, UType, JType, Byte, Bytes.